The disclosure relates in general to signal processing circuits and methods for source synchronization. In particular, the disclosure relates to signal processing circuits and methods for a double data rate (DDR) synchronous dynamic random access memory (SDRAM).
Certain types of memory devices generate a clock strobe signal having edges aligned with changes in the read data. A DDR SDRAM transfers data on each rising and falling edge of the clock strobe signal, thereby transferring two data words per clock cycle.
A read data synchronization circuit is often used to coordinate the transfer of data to and from a memory device, such as a DDR SDRAM. The read data synchronization circuit provides a local clock signal to the memory device to synchronize read and write operations. The clock strobe signal generated by the memory device with the read data has predefined phase constraints with respect to the local clock signal provided by the read data synchronization circuit. The read data synchronization circuit uses the clock strobe signal to determine when the read data is valid and can therefore be latched. The times at which the read data is latched are preferably synchronized relative to the clock strobe signal so as to latch the read data in the middle of the valid data window.
In normal operation, the memory controller can initiate a READ operation by issuing a READ command to the DDR SDRAM. In response, the DDR SDRAM will retrieve a predetermined portion of the data stored therein beginning at the particular address specified in the READ command. When ready to transmit the retrieved data, the DDR SDRAM will first generate the DQS preamble, then transmit the data, edge-aligned with both the rising and falling edges of DQS, and, finally, generate the DQS postamble. This sequence, however, is problematic when noise is introduced into the DQS signal. The memory controller can be operative to mistakenly receive the noise introduced DQS signal and consider the noise introduced DQS signal as the real DQS. The memory controller reacts prematurely and captures spurious data. In the other words, it fails to receive the actual data. If DQS is introduced the noise generating from problems of, the system PCB, interference of other signals, or DDR memory, some state machines will enter a false state and system crash due to abnormal access of memory.
This particular problem becomes increasingly serious as system clock rates rise in subsequent generations of DDR devices. Given the inherent difficulty in coordinating two electronic circuits physically located on separate chips, e.g., the DDR SDRAM and the memory controller, there may be no completely satisfactory solution for such inter-chip transactions, short of using the mixed-signal clock forwarding/recovery techniques common in high-speed telecommunication devices. A alternative solution is required to improve noise immunity in systems having DDR SDRAMs.
U.S. Pat. No. 6,785,189 to Jacobs provides a method and apparatus for improving noise immunity in a DDR SDRAM system. FIG. 1 is a block diagram disclosed by Jacobs.
Jacobs discloses a DQS qualifying circuit to frame the DQS from DDR SDRAM. The DQSQ frame generator 12 includes 2 dedicated pins and a dummy load, which should be equal to the load of DDR SDRAM. The DQSQ frame generator 12 transmits a DQS qualifying signal DQSQ from one pin, and receives a delayed DQS qualifying signal from existing controller circuits 14 after a certain fly time on PC board, equal to the fly time of DQS signal. Thus, the memory controller of Jacobs uses the delayed DQS qualifying signal to frame the DQS signal from DDR SDRAM 16.